1. Field of the Invention
This present invention relates to a cell structure for a Metal Insulator Semiconductor Dynamic Random Access Memory (hereinafter simply abbreviated as MIS DRAM) constructed in combination by one-transistor and one-capacitor and also to a method for manufacturing the same.
2. Related Art
A conventional memory cell structure for DRAMs is disclosed, for example, in Japanese Laid-open Patent Publication Number 60-225462. FIG. 1 shows such a conventional memory structure utilizing a trench.
A capacitor 20 is constituted by a capacitor electrode 5, a dielectric film 6 and a plate electrode 7, all of which are contained in a trench 2 formed in a silicon substrate 1. The capacitor 20 is electrically isolated from the substrate 1 by forming an oxide film 3 therebetween. Adjacent to the capacitor is formed a switching transistor 30 comprising diffusion layers 10, 11, a gate oxide film 8 and a gate electrode 9. The capacitor electrode 5 is electrically connected to one of the diffusion layer 10 of the switching transistor 30 at a contact region 4.
An inter-layer insulating film 12 is formed to coat the entire surface of the above constructed structure and a contact hole 13 is opened at a prescribed position for interconnection. A bit line 14 is formed on the inter-layer insulating film 12 so as to be connected through a contact hole 13 to the other diffusion layer 11. The gate electrode 9 of the switching transistor 30 extends in a direction vertical to the sectional view of the paper and constitutes a word line. A passivation film 15 is finally formed to coat the entire structure.
Another conventional cell structure has been proposed entitled as "BURIED STORAGE ELECTRODE (BSE) CELL FOR MEGABIT DRAMS" at pp 710-713, IEDM 85, 1985, IEEE.
The BSE cell is featured with a trench capacitor, similar to the other vertically structured memory cell described above so far, but differs from it in that the plate electrode is in the substrate whereas the charge storage electrode is in the buffed polysilicon which has been refilled into the capacitor trench. The buried polysilicon is connected to the diffusion region of the switching transistor just adjacent to the capacitor trench. Most portions of the capacitor trench penetrate deep into the p.sup.++ substrate. Key steps of BSE cell fabrication are described as follows:
(a) The shallow trench for isolation, filled with an insulating material, is formed within the p-type epitaxial layer in the isolation region. Then, deep trenches for the capacitor are dug down into the p.sup.++ substrate by means of reactive ion etching.
(b) A capacitor dielectric film is formed on the trench surface. Then, the trench is filled with conductive polysilicon. The polysilicon deposited outside of the trench is etched away through an etch-back process for planarization.
(c) After opening windows in the dielectric film just adjacent to the capacitor trench for n.sup.+ contact region formation, a polysilicon film is deposited. Then, phosphorus diffusion follows to dope the polysilicon and to diffuse phosphorus simultaneously into the epitaxial layer to form the n.sup.+ contact region. The buried polysilicon in the trench is electrically connected to the n.sup.+ contact region which is connected in turn to a contact electrode of the switching transistor. The polysilicon is then delineated using reactive ion etching and oxidized on its surface layer.
(d) The switching transistor formation and aluminum metalization are performed by using conventional process steps to form word lines and bit lines.
Among the above described conventional structures, the former one has the following shortcomings.
(1) The effective inner surface area of the trench, which can be utilized as a capacitor, decreases because the oxide for isolation and the capacitor electrodes are all formed in the trench. For example, the effective inner width of the trench becomes 0.2 .mu.m if the oxide and the capacitor electrode are 100 nm, respectively, in thickness even though the trench hole has a width of 0.6 .mu.m. Accordingly, a sufficient amount of capacitance can not be achieved when one attempts to shrink the cell.
(2) The contact region, which is disposed horizontally on the surface of the substrate between the trench capacitor and the switching transistor, may restrict further scale shrinkage. In addition, it is required to have some allowance between the contact region and the gate electrode, which also causes further restriction of the scale shrinkage.
(3) A leakage current may be generated between the capacitor electrode and the silicon substrate due to a parasitic MOS structure constructed at the side wall of the trench, thereby destroying information stored in the memory cell. Although the latter one can overcome the above mentioned three shortcomings, there still remains the following shortcomings.
Since the MIS transistor is formed in the epitaxial p.sup.+ layer on the heavily doped p.sup.++ substrate, depletion layer extension from the diffusion layers, i.e., the drain and source regions, is still thick and there cannot be accomplished a complete depletion type MIS transistor which improves sub-threshold characteristics remarkably and reveals better off-characteristics with a low threshold voltage.